june 2011 ?2011 fairchild semiconductor corporation FDMA3028N rev.c2 www.fairchildsemi.com 1 FDMA3028N dual n-channel powertrench ? mosfet FDMA3028N dual n-channel powertrench ? mosfet 30 v, 3.8 a, 68 m features ? max r ds(on) = 68 m at v gs = 4.5 v, i d = 3.8 a ? max r ds(on) = 88 m at v gs = 2.5 v, i d = 3.4 a ? max r ds(on) = 123 m at v gs = 1.8 v, i d = 2.9 a ? low profile - 0.8 mm maximum - in the new package microfet 2x2 mm ? rohs compliant general description this device is designed specifically as a si ngle package solution for dual switching requirements in cellular handset and other ultra-portable applications. it features two independent n-channel mosfets with low on-state resistance for minimum conduction losses. the micr ofet 2x2 package offers exceptional thermal performance fo r its physical size and is well suited to linear mode applications. mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 30 v v gs gate to source voltage 12 v i d drain current -continuous (note 1a) 3.8 a -pulsed 16 p d power dissipation (note 1a) 1.5 w power dissipation (note 1b) 0.7 t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance for single oper ation, junction to ambient (note 1a) 86 c/w thermal resistance for single oper ation, junction to ambient (note 1b) 173 thermal resistance for dual operation, j unction to ambient (note 1c) 69 thermal resistance for dual operation, junction to ambient (note 1d) 151 thermal resistance for single operation, junction to ambient (note 1e) 160 thermal resistance for dual operation, j unction to ambient (note 1f) 133 device marking device package reel size tape width quantity 328 FDMA3028N microfet 2x2 7 ?? 8 mm 3000 units g2 s1 g1 d2 d1 s2 s1 g1 d2 s2 microfet 2x2 d1 g2 pin 1 d1 d2 1 2 3 6 5 4 top bottom
www.fairchildsemi.com 2 ?2011 fairchild semiconductor corporation FDMA3028N rev.c2 FDMA3028N dual n-channel powertrench ? mosfet electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 30 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 23 mv/c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v 1 a i gss gate to source leakage current v gs = 12 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 0.6 0.9 1.5 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -3 mv/c r ds(on) static drain to source on resistance v gs = 4.5 v, i d = 3.8 a 46 68 m v gs = 2.5 v, i d = 3.4 a 56 88 v gs = 1.8 v, i d = 2.9 a 80 123 v gs = 4.5 v, i d = 3.8 a, t j = 125 c 72 108 g fs forward transconductance v ds = 5 v, i d = 3.8 a 15 s c iss input capacitance v ds = 15 v, v gs = 0 v, f = 1 mhz 282 375 pf c oss output capacitance 40 55 pf c rss reverse transfer capacitance 29 45 pf r g gate resistance 2.4 t d(on) turn-on delay time v dd = 15 v, i d = 3.8 a, v gs = 4.5 v, r gen = 6 5.3 11 ns t r rise time 310ns t d(off) turn-off delay time 15 27 ns t f fall time 2.5 10 ns q g(tot) total gate charge v dd = 15 v, i d = 3.8 a v gs = 5 v 3.7 5.2 nc q gs gate to source charge 0.4 nc q gd gate to drain ?miller? charge 1 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 1.3 a (note 2) 0.7 1.2 v t rr reverse recovery time i f = 3.8 a, di/dt = 100 a/ s 12 22 ns q rr reverse recovery charge 3.3 10 nc
www.fairchildsemi.com 3 ?2011 fairchild semiconductor corporation FDMA3028N rev.c2 FDMA3028N dual n-channel powertrench ? mosfet electrical characteristics t j = 25 c unless otherwise noted notes: 1. r ja is determined with the device mounted on a 1 in 2 oz. copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ja is determined by the user's board design. (a) r ja = 86 c/w when mounted on a 1 in 2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick pcb. for single operation. (b) r ja = 173 c/w when mounted on a minimum pad of 2 oz copper. for single operation. (c) r ja = 69 o c/w when mounted on a 1 in 2 pad of 2 oz copper, 1.5 ? x 1.5 ? x 0.062 ? thick pcb. for dual operation. (d) r ja = 151 o c/w when mounted on a minimum pad of 2 oz copper. for dual operation. (e) r ja = 160 o c/w when mounted on a 30mm 2 pad of 2 oz copper. for single operation. (f) r ja = 133 o c/w when mounted on a 30mm 2 pad of 2 oz copper. for dual operation. 2. pulse test : pulse width < 300 us, duty cycle < 2.0% a. 86 c/w when mounted on a 1 in 2 pad of 2 oz copper b. 173 c/w when mounted on a minimum pad of 2 oz copper c. 69 c/w when mounted on a 1 in 2 pad of 2 oz copper d. 151 c/w when mounted on a minimum pad of 2 oz copper e. 160 c/w when mounted on 30 mm 2 p ad of 2 oz co pp er f. 133 c/w when mounted on 30mm 2 of 2 oz copper
www.fairchildsemi.com 4 ?2011 fairchild semiconductor corporation FDMA3028N rev.c2 FDMA3028N dual n-channel powertrench ? mosfet typical characteristics t j = 25c unless otherwise noted figure 1. 0.0 0.5 1.0 1.5 2.0 0 4 8 12 16 v gs = 3.5 v v gs = 1.8 v v gs = 4.5 v v gs =2.5 v pulse duration = 80 p s duty cycle = 0.5%max v gs = 3 v i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0481 21 6 0.5 1.0 1.5 2.0 2.5 v gs = 4.5 v pulse duration = 80 p s duty cycle = 0.5%max normalized drain to source on-resistance i d , drain current(a) v gs = 3 v v gs = 2.5 v v gs = 1.8 v v gs = 3.5 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 3.8 a v gs = 4.5 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 50 100 150 200 t j = 125 o c i d = 3.8 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 0123 0 4 8 12 16 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 20 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
www.fairchildsemi.com 5 ?2011 fairchild semiconductor corporation FDMA3028N rev.c2 FDMA3028N dual n-channel powertrench ? mosfet figure 7. 01234 0 1 2 3 4 5 i d = 3.8 a v dd = 20 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 15 v gate charge characteristics figure 8. 0.1 1 10 30 10 100 500 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.1 1 10 100 0.01 0.1 1 10 20 100 p s 10 ms 10 s 100 ms dc 1 s 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 173 o c/w t a = 25 o c f o r w a r d b i a s s a f e operating area figure 10. 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.5 1 10 100 single pulse r t ja = 173 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e ma x i m u m power dissipation figure 11. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.005 0.01 0.1 1 2 d = 0.5 0.2 0.1 0.05 0.02 0.01 single pulse r t ja = 173 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a typical characteristics t j = 25c unless otherwise noted
www.fairchildsemi.com 6 ?2011 fairchild semiconductor corporation FDMA3028N rev.c2 FDMA3028N dual n-channel powertrench ? mosfet dimensional outline and pad layout
FDMA3028N dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 7 www.fairchildsemi.com FDMA3028N rev.c2 anti-counterfeiting policy fairchild semiconductor corporation?s anti-counterfeiting policy. fairchild?s anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support . counterfeiting of semiconductor parts is a growing problem in th e industry. all manufactures of semiconductor products are expe riencing counterfeiting of their parts. customers who inadvertently purchase counterfeit parts ex perience many problems such as loss of brand reputation, substa ndard performance, failed application, and increased cost of production and manufacturing dela ys. fairchild is taking strong measures to protect ourselve s and our customers from the proliferation of counterfeit parts. fairchild strongly encourages customers to purchase fairchild parts either directly from fa irchild or from authorized fairchild distributors who are listed by country on our web page cited above . products customers buy either from fairchild directly or fr om authorized fairchild distributors are genuine parts, have full traceability, meet fairchild?s quality standards for handing and storage and provide access to fairchild?s full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and wi ll appropriately address and warranty issues that may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from unau thorized sources. fairchild is committed to combat this global problem and encourage our customer s to do their part in stopping th is practice by buying direct or from authorized distributors. ? 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